Modern digital integrated circuit devices are achieving very high data processing speeds. For example, many widely used serial communication integrated circuit devices routinely operate at data I/O rates of multi-gigabits per second (Gbps). Such ever increasing data rates have placed ever increasing demands on the automatic test equipment (ATE) used to test the devices. As operating speeds have increased, higher and higher ATE test timing accuracy is required. For example, to properly test I/O signals of a multi-gigabit signal, the ATE must reliably and accurately place test strobe edges for the signal with pico-second accuracy.
Prior art conventional ATE methods are loosing their ability to keep pace with the edge placement accuracy requirements of high performance integrated circuit devices. One reason for the deficiency of the prior art is the fact that the conventional timing calibration error mechanisms do not accurately apply to high speed applications. Assumptions about the error mechanisms for a conventional device-under-test (DUT) are increasingly inaccurate as signal data rates increase into the mult-Gbps range.
For example, the basic prior art deskew calibration method is acceptably accurate to calibrate the same speed grade ATE pins at the driver/comparator junctions, if data dependent timing error/jitter (DDJ) is negligibly small. DDJ is, however, one of the major error sources in multi-Gbps testing, and therefore needs to be properly accounted for, and calibrated out, for higher timing accuracy. For DDJ calibration, at-speed calibration measurement is essentially required, and therefore the prior art calibration methods, which necessitate calibration measurements at low speed, are not applicable.
Another problem is the fact that as signal data rates increase into the multi-Gbps range, the conventional prior art practice of modeling the ATE to DUT signals paths as simple transmission lines is no longer valid. At the multi-Gbps speeds, a number of different error sources quickly become significant and can no longer be ignored. Such error sources include, for example, DDJ timing error, pin-to-pin skew, and calibration errors at the DUT. These problems render the prior art testing methodology insufficient for modern high speed, high performance integrated circuit devices.
Thus what is required is a solution that can accurately and reliably test modern high speed integrated circuit devices. The required solution should be capable of accounting for error sources such as DDJ, pin-to-pin skew, and calibration errors in a testing and verification process for a high performance DUT. Another problem is the fact that as signal data rates increase into the multi-Gbps range, the conventional prior art practice of modeling the ATE to DUT signals paths as simple transmission lines with a few lumped parasitic capacitors and inductors is no longer valid.